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ICB1FL01G smart ballast control ic for fluorescent lamp ballasts never stop thinking. power management & supply preliminary datasheet version 1.5, june 2005
edition 2005-06-06 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen ? infineon technologies ag 1999. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted charac- teristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and co nditions and prices please contact your nearest infi- neon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http:// www.infineon.com ICB1FL01G revision history: 2005-06-06 datasheet previous version: 2005-05-19 page subjects (major change s since last revision) 25,26 min./ max values updated 29 add d10 we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com
type ordering code package ICB1FL01G q67045-a5088 pg-dso-18-1 ICB1FL01G pg-dso-18-1 preliminary datasheet version 1.5 3 june 2005 product highlights ? lowest count of external components ? hv-driver with coreless transformer technology ? improved reliability and minimized spread due to digital and optimized analog control functions features pfc ? discontinuous conduction mode pfc ? integrated compensation of pfc control loop ? adjustable pfc current limitation ? adjustable pfc bus voltage features lamp ballast inverter ? supports restart after lamp removal and end-of- life detection in multi-lamp topologies ? end-of-life (eol) detected by adjustable +/- thresholds of sensed lamp voltage ? rectifier effect detected by ratio of +/- amplitude of lamp voltage ? detection of different capacitive mode operations ? adjustable inverter overcurrent shutdown ? self-adaption of ignition time from 40ms to 235ms ? parameters adjustable by resistors only ? pb-free lead plating; rohs compliant smart ballast control ic for fluorescent la mp ballasts description the smart ballast ic is designed to control a fluorescent lamp ballast including a discontinuous conduction mode power factor correction (pfc), a lamp inverter control and a high voltage level shift half-bridge driver. the application requires a minimum of external components. there are integrated low pass filters and an internal compensation for the pfc voltage loop control. preheating time is adjustable by a single resistor only in the range between 0 and 2000ms. in the same way the preheating frequency and run frequency are set by resistors only. the control concept covers requirements for t5 lamp ballasts such as detection of end-of-life and detection of capacitive mode operation and other protection measures even in multilamp topologies. ICB1FL01G is easy to use and easy to design and therefore a basis for a cost effective solution for fluorescent lamp ballasts. rfrun rfph rtph vcc pfczcd pfcgd pfcvs pfccs hsgd hsvcc hsgnd lsgd lscs lvs2 lvs1 res gnd 90 ... 270 v ac typical application ICB1FL01G rfrun rfph rtph vcc pfczcd pfcgd pfcvs pfccs hsgd hsvcc hsgnd lsgd lscs lvs2 lvs1 res gnd 90 ... 270 v ac typical application ICB1FL01G
ICB1FL01G table of contents page preliminary datasheet version 1.5 4 june 2005 1 pin configuration and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.1 pin configuration pg-dso-18-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2 blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.1 typical operating levels during start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.2 pfc preconverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.3 typical operating levels during start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.4 detection of end-of-life and rectifier effect . . . . . . . . . . . . . . . . . . . . . . . .14 3.5 detection of capacitive mode operating conditions . . . . . . . . . . . . . . . . . . .15 3.6 interruption of operation and restart after lamp removal . . . . . . . . . . . . .16 4 state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 5 protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 6.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 6.2 operating range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 6.3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 6.3.1 power supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 6.3.2 pfc section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 6.3.2.1 pfc current sense (pfccs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 6.3.2.2 pfc zero current detector (pfczcd) . . . . . . . . . . . . . . . . . . . . . . . .23 6.3.2.3 pfc bus voltage sense (pfcvs) . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 6.3.2.4 pfc pwm generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 6.3.2.5 pfc gate drive (pfcgd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 6.3.3 inverter section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 6.3.3.1 inverter control (rfrun, rfph, rtph) . . . . . . . . . . . . . . . . . . . . . .25 6.3.3.2 inverter low side current sense (lscs) . . . . . . . . . . . . . . . . . . . . . .25 6.3.3.3 restart after lamp removal (res) . . . . . . . . . . . . . . . . . . . . . . . . . . .26 6.3.3.4 lamp voltage sense (lvs1, lvs2) . . . . . . . . . . . . . . . . . . . . . . . . . .26 6.3.3.5 inverter low side gate drive (lsgd) . . . . . . . . . . . . . . . . . . . . . . . . .27 6.3.3.6 inverter high side gate drive (hsgd) . . . . . . . . . . . . . . . . . . . . . . . .28 7 application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 7.1 operating behaviour of a ballast for a single fluorescent lamp . . . . . . . . .29 7.2 design equations of a ballast application . . . . . . . . . . . . . . . . . . . . . . . . . .30 7.3 multilamp ballast topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 8 outline dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
preliminary datasheet version 1.5 5 june 2005 ICB1FL01G pin configuration and description 1 pin configuration and description 1.1 pin configuration pg-dso-18-1 1.2 pin description lscs (low side current sense, pin 1 ) this pin is directly connected to the shunt resistor which is located between the source terminal of the low-side mosfet of the inverter and ground. internal clamping structures and filtering measures allow for sensing the source current of the low-side inverter mosfet without additional filter components. there is a first threshold of 0,8v, which provides a couple of increasing steps of frequency during ignition mode, if exceeded by the sensed current signal for a time longer than 250ns. if the sensed current signal exceeds a second threshold of 1,6v for longer than 400ns during all operating modes, a latched shut down of the ic will be the result. lsgd (low side gate drive, pin 2) the gate of the low-side mosfet in a half-bridge inverter topology is controlled by this pin. there is an active l-level during uvlo (undervoltage lockout) and a limitation of the max. h-level at 11v during normal operation. turning on the mosfet softly (with reduced di drain /dt), the gate drive voltage rises within 220ns from l-level to h-level. the fall time of the gate drive voltage is less than 50ns in order to turn off quickly. this measure produces different switching speeds during turn-on and turn-off as it is usually achieved with a diode in parallel to a resistor in the gate drive loop. it is recommended to use a resistor of about 15ohm between drive pin and gate in order to avoid oscillations and in order to shift the power dissipation of discharging the gate capacitance into this resistor. the dead time between lsgd signal and hsgd signal is 1800ns typically. vcc (supply voltage, pin 3) this pin provides the power supply of the ground related section of the ic. there is a turn-on threshold at 14v and an uvlo threshold at 10,5v. upper supply voltage level is limited internally at 16v (2ma). for higher current levels an external zener diode is required. current consumption during uvlo and during fault mode is less than 150 a. a ceramic capacitor close to the supply and gnd pin is required in order to act as a low-impedance power source for gate drive and logic signal currents. gnd (ground, pin 4) this pin is connected to ground and represents the ground level of the ic for supply voltage, gate drive and sense signals. pin symbol function 1 lscs low side current sense (inverter) 2 lsgd low side gate drive (inverter) 3 vcc supply voltage 4 gnd controller ground 5 pfcgd pfc gate drive 6 pfccs pfc current sense 7 pfczcd pfc zero current detector 8 pfcvs pfc voltage sense 9 rfrun set r for run frequency 10 rfph set r for preheating frequency 11 rtph set r for preheating time 12 res restart after lamp removal 13 lvs1 lamp voltage sense 1 14 lvs2 lamp voltage sense 2 15 n.e. not existing 16 n.e. not existing 17 hsgnd high side ground 18 hsvcc high side supply voltage 19 hsgd high side gate drive 20 hsgnd high side ground hsvcc hsgnd rfph res lvs1 pg-dso-18-1 (300mil) lvs2 rfrun pfcvs pfczcd ICB1FL01G gnd hsgd lsgd pfcgd lscs pfccs vcc rtph hsgnd 10 9 8 7 4 2 5 1 6 3 11 12 13 14 17 19 16 20 15 18
ICB1FL01G pin configuration and description preliminary datasheet version 1.5 6 june 2005 pfcgd (pfc gate drive, pin 5) the gate of the mosfet in the pfc preconverter designed in boost topology is controlled by this pin. there is an active l-level during uvlo and a limitation of the max. h-level at 11v during normal operation. turning on the mosfet softly (with a reduced di drain / dt), the gate drive voltage rises within 220ns from l- level to h-level. the fall time of the gate voltage is less than 50ns in order to turn off quickly. a resistor of about 10ohm between drive pin and gate in order to avoid oscillations and in order to shift the power dissipation of discharging the gate capacitance into this resistor is recommended. the pfc section of the ic controls a boost converter as a pfc preconverter in discontinuous conduction mode (dcm). typically the control starts with gate drive pulses with an on-time of 1 s increasing up to 24 s and a off-time of 40 s. as soon as a sufficient zcd (zero current detector) signal is available, the operating mode changes from a fixed frequent operation to an operation with variable frequency. during rated and medium load conditions we get an operation with critical conduction mode (critcm), that means triangular shaped currents in the boost converter choke without gaps when reaching the zero level and variable operating frequency. during light load (detected by the internal error amplifier) we get an operation with discontinuous conduction mode (dcm), that means triangular shaped currents in the boost converter choke with gaps when reaching the zero level and variable operating frequency in order to avoid steps in the consumed line current. pfccs (pfc current sense, pin 6) the voltage drop across a shunt resistor located between source of the pfc mosfet and gnd is sensed with this pin. if the level exceeds a threshold of 1v for longer than 260ns the pfc gate drive is turned off as long as the zcd (zero current detector) enables a new cycle. if there is no zcd signal available within 40s after turn-off of the pfc gate drive, a new cycle is initiated from an internal start-up timer. pfczcd (pfc zero current detection, pin 7) this pin senses the point of time when the current through the boost inductor becomes zero during off- time of the pfc mosfet in order to initiate a new cycle. the moment of interest appears when the voltage of the separate zcd winding changes from positive to negative level which represents a voltage of zero at the inductor windings and therefore the end of current flow from lower input voltage level to higher output voltage level. there is a threshold with hysteresis, for increasing voltage a level of 1,5v, for decreasing voltage a level of 0,5v, that detects the change of inductor voltage. a resistor connected between zcd winding and sense input limits the sink and source current of the sense pin, when the voltage of the zcd winding exceeds the internal clamping levels (6,3v and -2,9v @ 4ma) of the ic. if the sensed level of the zcd winding is not sufficient (e.g. during start-up), an internal start-up timer will initiate a new cycle every 40 s after turn-off of the pfc gate drive. pfcvs (pfc voltage sense, pin 8) the intermediate circuit voltage (bus voltage) at the smoothing capacitor is sensed by a resistive divider at this pin. the internal reference voltage for rated bus voltage is 2,5v. there are further thresholds at 0,375v (15% of rated bus voltage), 1,83v (73% of rated bus voltage) and 2,725v (109% of rated bus voltage) for detecting open control loop, undervoltage and overvoltage. rfrun (set r for run frequency, pin 9) a resistor from this pin to ground sets the operating frequency of the inverter during run mode. typical run frequency range is 20khz to 100khz. the set resistor r rfrun can be calculated based on the run frequency f run according to the equation rfph (set r for preheating frequency, pin 10) a resistor from this pin to ground sets together with the resistor at pin 9 the operating frequency of the inverter during preheat mode. typical preheat frequency range is run frequency (as a minimum) to 150khz. the set resistor r rfph can be calculated based on the preheat frequency f ph and the resistor r rfrun according to the equation: the total value of both resistors r rfph and r rfrun switched in parallel should not be less than 3,3kohm. rtph (set r for preheating time, pin 11) a resistor from this pin to ground sets the preheating time of the inverter during preheat mode. a set resistor range from zero to 20kohm corresponds to a range of preheating time from zero to 2000ms subdivided in 127 steps. r rfrun 510 8 ? hz ? f run ----------------------------- = r rfph r rfrun f ph r rfrun ? 510 8 ? hz ? ---------------------------------------- 1 ? ------------------------------------------------- - =
ICB1FL01G pin configuration and description preliminary datasheet version 1.5 7 june 2005 res (restart after lamp removal, pin 12) a source current out of this pin via resistor and filament to ground monitors the existence of the low-side filament of the fluorescent lamp for restart after lamp removal. a capacitor from this pin directly to ground eliminates a superimposed ac voltage that is generated as a voltage drop across the low-side filament. with a second sense resistor the filament of a paralleled lamp can be included into the lamp removal sense. during typical start-up with connected filaments of the lamp a current source i res3 (20a) is active as long as vcc> 10,5v and v res < v resc1 (1,6v). an open low- side filament is detected, when v res > v resc1 . such a condition will prevent the start-up of the ic. in addition the comparator threshold is set to v resc2 (1,3v) and the current source changes to i res4 (17a). now the system is waiting for a voltage level lower than v resc2 at the res-pin that indicates a connected low-side filament, which will enable the start-up of the ic. an open high-side filament is detected when there is no sink current i lvssink (12a) into both of the lvs-pins before the v cc start-up threshold is reached. under these conditions the current source at the res-pin is i res1 (41a) as long as vcc> 10,5v and v res < v resc1 (1,6v) and the current source is i res2 (34a) when the threshold has changed to v resc2 (1,3v). in this way the detection of the high-side filament is mirrored to the levels on the res-pin. finally there is a delay function implemented at the res-pin. when a fault condition happens e.g. by an end-of-life criteria the inverter is turned-off. in some topologies a transient ac lamp voltage may occur immediately after shut down of the gate drives which could be interpreted as a lamp removal. in order to generate a delay for the detection of a lamp removal the capacitor at the res-pin is charged by the i res3 (20a) current source up to the threshold v resc1 (1,6v) and discharged by an internal resistor r resdisch , which operates in parallel to the external sense resistor at this pin, to the threshold v resc3 (0,375v). the total delay amounts to 32 of these cycles, which corresponds to a delay time between 30ms to 100ms dependent on capacitor value. in addition this pin is applied to sense capacitive mode operation by use of a further capacitor connected from this pin to the nod of the high-side mosfet?s source terminal and the low-side mosfet?s drain terminal. the sense capacitor and the filter capacitor are acting as a capacitive voltage divide r that allows for detecting voltage slopes versus timing sequence and therefore indicating capacitive mode operation. a typical ratio of the capacitive divider is 410v/2,2v which results in the capacitor values e.g. of 10nf and 53pf (56pf). lvs1 (lamp voltage sense 1, pin 13) before the ic enters the softstart mode this pin has to sense a sink current above 22 a which is fed via resistors from the bus voltage across the high-side filament of the fluorescent lamp in order to monitor the existence of the filament for restart after lamp removal. together with lvs2 (pin 14) and res (pin 12) the ic can monitor the lamp removal of totally 4 lamps. during run mode the lamp voltage is sensed by the ac current fed into this pin via resistors. exceeding one of the two thresholds of either +230 a or -230 a cycle by cycle for longer than 500ms, the interpreta tion of this event is a failure due to eol (end-of-life). a rectifier effect is assumed if the ratio of the sequence of positive and negative amplitudes is above 1,15 or below 0,85 for longer than 500ms. a failure due to eol or rectifier effect changes the operating mode from run mode into a latched fault mode that stops the operation until a reset occurs by lamp removal or by cycle of power. if the functionality of this pin is not required (e.g. for single lamp designs) it can be disabled by connecting this pin to ground. lvs2 (lamp voltage sense 2, pin 14) same functionality as lvs1 (pin 13) for monitoring a paralleled lamp circuit. hsgnd (high side ground, pin 17) this pin is connected to the source terminal of the high-side mosfet, which is also the nod of high-side and low-side mosfet. this pin represents the floating ground level of the high-side driver and high-side supply. hsvcc (high side supply voltage, pin 18) this pin provides the power supply of the high-side ground related section of the ic. an external capacitor between pin 15 and 16 acts like a floating battery which has to be recharged cycle by cycle via high voltage diode from low-side supply voltage during on-time of the low-side mosfet. there is an uvlo threshold with hysteresis that enables high-side section at 10,1v and disables it at 8,4v. hsgd (high side gate drive, pin 19) the gate of the high-side mosfet in a half-bridge inverter topology is controlled by this pin. there is an active l-level during uvlo and a limitation of the max. h-level at 11v during normal operation. the switching characteristics are the same as described for lsgd (pin 2). it is recommended to use a resistor of about 15ohm between drive pin and gate in order to avoid oscillations and in order to shift the power dissipation of discharging the gate capacitance into this resistor. the dead time between lsgd signal and hsgd signal is 1800ns typically. hsgnd (high side ground, pin 20) this pin is internally connected with pin 15.
ICB1FL01G blockdiagram preliminary datasheet version 1.5 8 june 2005 2 blockdiagram figure 1 simplified blockdiagram of ICB1FL01G 9 rfrun 8 pfcvs 10 rfph 11 rtph int. supply & g3 z1 16v @2ma vcc 5v 5s blank uvlo v th1 =14,0v v th2 =10,5v c2 v th =10,5v off_h vdd_good_h c1 powersupply s1 r1 rtph c1 t1 t2 phend_h 5,0v dac7 2,0v softstart and preheat mode other modes op bias cell1 5s blank preheat_timer oscillator i osc ? f osc s3 s1 r1 osc v r e f rfph rfrun t1 t2 i osc 2,5v preheat mode other modes other modes run mode dac7, dac4 = gnd during run mode, otherwise transient voltage levels (0..2,5v) 5,0v dac7 dac4 vco 2,5v dac7 op bias cell1 op bias cell2 op bias cell3 s2 vcc op1 r1 a v = 2.5 r2 v ref = 2,50v 8-bit adc c1 v th1 = 2,725v v th2 = 2,625v c2 v th = 1,83v c3 v th = 0,375v vbus overvoltage vbus undervoltage vbus open loop detect digital loop control pfc_pwm_in 5s blank 5s blank 5s blank pfc_vs end-of-life 2 lv s2 14 lvs2 lvs_2 spi for test mode bandgap vref=2.5v master clock digital sequential control dac4 dac7 dsc osc phend_h mclock_spi power_down_l & g6 c3 c4 d2 d1 vcc 5v end-of-life 1 dq & g2 en i1 = 5a power_down_l h = on l = off eoloff_l eolactive_h linsert_h g3 en=l => status latched +230a -230a 1 g5 c1 12a c2 2,0v d3 1 g1 1 g4 i lvs lvs1 13 lvs1 > 1,2?.... => q = h = 0,85..1,2 => q = l < 0,85?... => q = h q off_h v peak (n+1) v peak (n) = lvs_1 t1 n i lvs peak rectification n+2 n+1 v peak (n+1) v peak (n) end-of-life 1 end-of-life 2 capacitive load 1 open filament vbus overvoltage inverter overcurrent up & down counter min.duration of effect: 500ms capacitive load 2 operation above run frequency 1 error_logic min.duration of effect: 400ns min.duration of effect: 605s 235ms after end of preheat mode 1 r s q q fault latch 1 power_down_l lvs1_l lvs2_l off_h lamp_insert_h uvlo_l open_loop_l & 1 c5 0,375v c4 c3 1,3v 1,6v 54k 5,0v t1 c1 c1 3,2v 0,2v inv1 t1 c2 d q d q g1 d q g2 g3 12 res 5 s blank 5 s blank 5 s blank i3= 20a; v res < 1,6v; v cc > 10,5v; i lvs > 12a; or during run mode i1= 41a; v res < 1,6v; v cc > 10,5v; i lvs < 12a; i4= 17a; v res > 1,6v; v cc > 10,5v; i lvs > 12a; i2= 34a; v res > 1,6v; v cc > 10,5v; i lvs < 12a; i5= 41a & 0a alternating for 32 cycles as a delay; v ds capacitive load detection cap load1 v ds cap load2 capload-res lamp insert detection for vres < 1,6v during power down. delay generator for activating lamp removal after fault latch is set. lsgdin_h hsgdin_h capload1 capload2 open_filament lvs2 lvs1 lamp _insert_h & d1 pfccs c1 1.0v 260ns blank c2 v th1 =1,5v v th2 =0,5v d2 r1 r2 d3 5,0v pfc_zcd pfc_clim 6 pfccs 7 pfczcd d1 start-up timer off-time 40s pfc pwm & control pfcpwm pfc_pwm_in pfcgdin dsc pfcgd z1 1 g1 t2 t1 d2 d1 vcc pfcgdin 5 pfcgd slope control z1 =12v 0 220ns t v gate 1,8s dead time pwm inverter invpwm dsc ls hs c1 c2 0,8v 1,6v 250ns blank 400ns blank inv_oc ign-lim invclim 1 lscs 2 lsgd 3 4 gnd lsgd z1 1 g1 t2 t1 d2 d1 vcc ls slope control z1 =12v 0 220ns t v gate hsgd z1 1 g1 d2 d1 t1 t2 hsvcc 19 18 17 hsgd hsgnd slope control z1 =12v 0 220ns t v gate hs coreless t.
ICB1FL01G functional description preliminary datasheet version 1.5 9 june 2005 3 functional description 3.1 typical operating levels during start-up the control of the ballast should be able to start the operation within less than 100ms. therefor the current consumption of the ic is less than 150a during uvlo. with a small start-up capacitor (about 1f) and a power supply, that feeds within 100s (charge pump of the inverter) the ic can cover this feature. as long as the vcc is less than 10,5v, the current c onsumption is typically 80a. above a vcc voltage level of 10,5v the ic checks whether the lamp(s) are assembled by detecting a current across the filaments. the low-side filament is checked from a source current (20a typ.) out of pin res, that produces a voltage drop at the sense resistor, which is connected via low-side filament to ground. an open filament is detected, when the voltage level at pin res is above 1,6v. the high-side filament (or the high-side of a series topology) is checked by a current (12a typ.) into the lvs pin. an open high-side filament causes a higher source current (41a / 34a typ.) out of pin res in order to exceed the 1,6v threshold. if one of both filaments is not able to conduct the test current, the control circuit is disabled. the ic is enabled as soon as a sufficient current is detected across the filaments or the supply voltage drops below the uvlo threshold (10,5v) e.g. by turn-off and turn-on of mains switch. figure 2 progress of levels during a typical start-up. when the previous conditions are fulfilled, and vcc has reached the start-up threshold (14v), there is finally a check of the bus voltage. if the level is less than 15% of rated bus voltage, the ic is waiting in power down mode until the voltage increases. if the level is above 109% of rated bus voltage there is no gate drive, but an active ic. the supply voltage vcc will fall below the uvlo threshold and a new start-up attempt is initiated. as soon as start-up conditions are fulfilled the ic starts driving the inverter with the start-up frequency of 120khz. now the complete control including timers and the pfc control can be set in action. there are current limitation thresholds for pfc preconverter and ballast inverter equipped with spike filters. the pfc current limitation interrupts the on-time of the pfc mosfet if the voltage drop at shunt resistor exceeds 1v and restarts after next input from zcd. the inverter current limitation operates with a first threshold of 0,8v which increases the operating frequency during ignition mode if exceeded. a second threshold is provided at 1,6v that stops the whole control circuit and latches this event as a fault. v cc 14,0v 10,5v i vcc 80a 8ma + qgate v res 1,6v i res 20a i lvs >12a < +/- 2,5ma 3,2v uvlo start-up hysteresis ic active softstart t t t t t 150a 80a <3,2v 20a >12a
ICB1FL01G functional description preliminary datasheet version 1.5 10 june 2005 figure 3 start-up with ls filament broken and subsequent lamp removal. figure 4 start-up with hs filament broken and subsequent lamp removal. v cc 14,0v 10,5v i vcc 80a 8ma + qgate v res 1,6v i res 20a i lvs >12a 3,2v uvlo start-up hysteresis ic active softstart t t t t t < +/- 2,5ma 17a 34a 17a 20a 16,0v ls filament open hs filament closed lamp removal ls + hs open 1,3v power down signal t 20a 5,0v h v res > 1,3v 80a 150a >12a >12a <3,2v v cc 14,0v 10,5v i vcc 80a 8ma + qgate v res 1,6v i res 20a i lvs >12a 3,2v uvlo ic active softstart t t t t t < +/- 2,5ma 34a 34a 17a 20a 16,0v lamp removal ls + hs open v res > 1,3v 1,3v power down signal t 41a 5,0v h <3,2v 150a 80a start-up hysteresis hs filament open ls filament closed >12a 1,3v
ICB1FL01G functional description preliminary datasheet version 1.5 11 june 2005 3.2 pfc preconverter pfc is starting with a fixed frequent operation (ca. 25khz), beginning with an on-time of 1s and an off-time of 40s. the on-time is enlarged every 400s to a maximum on-time of 23s. the control switches over into critical conduction mode (critcm) operation as soon as a suffici ent zcd signal is available. there is an overvoltage threshold at 109% of rated bus voltage that stops pfc gate drive as long as the bus voltage has reached a level of 105% of rated bus voltage again. the compensation of the voltage control loop is completely integrated. the internal reference level of the bus voltage sense (pfcvs) is 2,5v with high accuracy. the pfc control operates in critcm in the range of 23s > on-time > 2,3s. for lower loads the control operates in discontinuous conduction mode (dcm) with an on-time down to 0,5s and an increasing off-time. with this control method the pfc preconverter covers a stable operation from 100% of load to 0,1% . figure 5 circuit diagram of the pfc preconverter section. overvoltage, undervoltage and open loop detection at pin pfcvs are sensed by analog comparators. the bus voltage loop control is provided by a 8bit sigma-delta a/d-converter with a sampling rate of 400s and a resolution of 4mv/bit. so a range of +/- 0,5v from the reference level of 2,50v is covered. the digital error signal has to pass a digital notch filter in order to suppress the ac voltage ripple of twice of the mains frequency. a subsequent error amplifier with pi characteristic cares for stable operation of the pfc preconverter. during ignition and pre-run mode the notch filter is bypassed in order to increase control loop reaction. the zero current detection is sensed by a separate pin pfczcd. the information of finished current flow during demagnetization is required in critcm and in dcm as we ll. the input is equipped with a special filtering, that covers a period of typically 500ns and is combined with a large hysteresis between the thresholds of typically 0,5v and 1,5v. in case of bad coupling between primary inductor winding and secondary zcd-winding an additional filtering by a capacitor at zcd pin might be necessary in order to avoid mistriggering by long lasting oscillations during switching slopes of the pfc mosfet. figure 6 structure of the mixed digital and analog control of pfc preconverter. rfrun rfph rtph vcc pfczcd pfcgd pfcvs pfccs hsgd hsvcc hsgnd lsgd lscs lvs2 lvs1 res gnd 90 ... 270 vac ICB1FL01G r1 r2 d1...4 l rfi l1 d5 q1 r8 r7 r3 r4 r6 d9 c1 c2 c3 r9 r5 r12 r13 c7 vbus vcc pfcvs pfcgd pfccs pfczcd pulse width generator gate driver overcurrent protection 1,0v +/-5% zcd 1,50v / 0,5v start-up clock 600khz pi loop control notch filter undervoltage 73% +/- 2,5% overvoltage 109% +/-2,0% open loop detection 15% +/- 20% ? -adc srate 400s res 4mv/bit reference 2,50v +/-1,5%
ICB1FL01G functional description preliminary datasheet version 1.5 12 june 2005 figure 7 relative output power and operating frequency of pfc control at vin = vout /2 versus control step. figure 8 on-time and operating frequency of pfc control at vin = vout /2 versus control step. discontinuous conduction mode <> critical conduction mode 0,1 1 10 100 0 32 64 96 128 160 192 224 256 digital control steps relative power % identification markings unfilled 1 10 100 1000 operating frequency (khz) at vin = vout/2 identification markings filled discontinuous conduction mode <> critical conduction mode 0 1 10 100 0 32 64 96 128 160 192 224 256 digital control steps on-time (s) identification markings unfilled 1 10 100 1000 operating frequency (khz) at vin = vout/2 identification markings filled
ICB1FL01G functional description preliminary datasheet version 1.5 13 june 2005 3.3 typical operating levels during start-up within 10ms after start-up the inverter shifts operating frequency from 120khz to the preheating frequency set by resistor at pin rfph. preheating time can be selected by programming resistor at rfph pin in steps of 17ms from 0ms to 2000ms. after preheating the operating frequency of the inverter is shifted downwards in 40ms typically to the run frequency. during this frequency shifting the voltage and current in the resonant circuit will rise when operating close to the resonant frequency with increasing voltage across the lamp. as soon as the lower current sense level (0,8v) is reached, the frequency shift downwards is stopped and increased by a couple of frequency steps in order to limit the current and the ignition voltage also. the procedure of shifting the operating frequency up and down in order to stay within the max ignition level is limited to a time frame of 235ms. if ther e is no ignition within this time the control is disabled and the status is latched as a fault mode. figure 9 typical variation of operating frequency and lamp voltage during start-up. figure 10 typical lamp voltage versus operating frequency due to load change of the resonant circuit. 65khz 50khz 40khz preheating ignition normal operation 120khz softstart frequency f , v lamp voltage 40-235ms t 10ms 0-2000ms pre-run 250ms typical variation of operating frequency during start-up softstart proceeds in 15 steps 650s according ? f ph = (120khz - f ph )/ 15steps. ignition proceeds in 127 steps 324s according ? f ign = (f ph - f run )/ 127steps. 0 100 200 300 400 500 600 700 800 900 1000 10000 100000 operating frequency lamp voltage ignition preheating after ignition run without load with load
ICB1FL01G functional description preliminary datasheet version 1.5 14 june 2005 3.4 detection of end-of-life and rectifier effect after ignition the lamp voltage breaks down to its run voltage level (typically 50vpeak to 300vpeak). reaching the run frequency there follows a time period of 250ms called pre-run mode, in which some of the monitoring features (eol1, eol2, cap.load1) are still disabled. in the subsequent run mode the end-of-life (eol) monitoring is enabled. the event end-of-life is detected by measuring the positive and negative peak level of the lamp voltage by a current fed into the lvs pin. if the sensed current exceeds 230a for longer than 500ms the status end-of- life is detected. furthermore the rectification effect (eol2) is also detected when the ratio of the positive and negative amplitude of the lamp voltage is above 1,15 or below 0,85 for longer than 500ms. the voltage ratio is dependent on the level of sensed current acc. fig. 13 and 14. if the end-of-life conditions are detected, the control is disabled and the status is latched as a failure mode. measuring the duration of incorrect operating conditions is done by a check every 4ms. if one of the fault conditions is existing, a count er counts up, if fault condition is not existing, the counter counts down. so we get an integration of the fault events that allows a very effective monitoring of strange operating conditions. figure 11 circuit diagram of the lamp inverter section. figure 12 sensed lamp voltage levels. rf run rf ph rt ph vcc pfczcd pfcgd pfcvs pfccs hsgd hsvcc hsgnd lsgd lscs lvs2 lvs1 res gnd ICB1FL01G vbus vcc d9 c2 r5 r12 r13 r10 r11 c4 c7 q2 q3 r14 r16 r15 r17 r18 r19 r20 c5 c6 c8 c9 c10 l2 d6 d7 d8 r30 d10 t + shut down level - shut down level - ignition level + ignition level + eol threshold - eol threshold iv l+peak i/iv l-peak i v lamp-run v lamp-ign 0
ICB1FL01G functional description preliminary datasheet version 1.5 15 june 2005 figure 13 maximum ratio of amplitudes versus sense current. figure 14 minimum ratio of amplitudes versus sense current. 3.5 detection of capacitive mode operating conditions if there happens a situation like an open resonant circuit (e.g. a sudden break of the tube) the voltage across the resonant capacitor and current through the shunt of the low-side inverter mosfet rise quickly. this event is detected by inverter current limitation (1,6v) and results in shut down of the control. this status is latched as a failure mode. in another kind of failure the operation of the inverter may leave the zero voltage switching (zvs) and move into capacitive mode operation or into operation below resonance. there are two different levels for capacitive mode detection implemented in the ic. a first criteria detects low deviations from zvs (capload1) and changes operation into fault mode, if this operation lasts longer than 500ms. for capload1 the same counter is used as for the end-of-life evaluation. 1,00 1,10 1,20 1,30 1,40 1,50 1,60 1,70 1,80 0 50 100 150 200 250 lamp voltage / sense resistor [ua] ratio of amplitudes (n+1)/n 0,20 0,30 0,40 0,50 0,60 0,70 0,80 0,90 1,00 0 50 100 150 200 250 lamp voltage / sense resistor [ua] ratio of amplitudes (n+1)/n
ICB1FL01G functional description preliminary datasheet version 1.5 16 june 2005 a second threshold detects severe deviations such as rectangular shapes of voltage during operation below resonance (capload2). then the inverter is turned off as so on as these conditions last longer than 605s and the ic changes over into fault mode. the evaluation of the failure condition is done by an up and down counter which samples the status every 40s. capload1 is sensed in the moment when low-side gate drive is turned on. if the voltage level at pin res is above the v rescap threshold (typ. 0,24v) related to the level v resllv , conditions of capload1 are assumed. capload2 is sensed in the moment when the high-side gate drive is turned on. if the voltage level at pin res is below the v rescap threshold related to the level v resllv , conditions of capload2 are assumed. as the reference level v resllv is a floating level, it is updated every on-time of the low-side mosfet. d10 limits voltage transients at pin res that can occur during removal of the lamp in run mode. figure 15 levels and points in time for detection of capload1 and capload2. 3.6 interruption of operation and restart after lamp removal in the event of a failing operation the fault latch is set after the specified reaction time (e.g. 500ms at eol). then the gate drives are shut down immediately, the control functions are disabled and the current consumption is reduced to a level of 150a (typically). vcc is clamped by internal zener diode to max 17,5v at 2ma. so the internal zener diode is only designed to limit vcc when fed from the start-up current, but not from the charge pump supply! the capacitor at pin res is discharged and charged during 32 cycles in order to generate a delay of several 10ms. the delay is implemented for avoiding malfunctions in detecting the lamp removal due to voltage transients that can occur after shut down. the reset of the fault latch happens after exceeding the 1,6v threshold at pin res and enabling the ic after lamp removal and subsequent decreasing voltage level at pin res below the 1,3v threshold. t t t t deadtime t capm 1 t capm 2 v dsls i dls v res v resllv v res5 gate hs gate ls
ICB1FL01G functional description preliminary datasheet version 1.5 17 june 2005 the status failure mode is kept as long until a lamp removal is detected (interruption of current across filaments and detection of the return of the current) or the supply voltage drops below uvlo. after a break down of the supply voltage below the undervoltage lockout (uvlo) threshold the ic resets any failure latch and will try to restart as soon as vcc exceeds the start-up threshold. an undervoltage (75%) of the bus voltage will not be latched as a fault condition. if the undervoltage lasts longer than 80s the gate drives are switched off and the ic tries to restart after a vcc hysteresis has been passed. figure 16 interruption of operation by a fault condition and subsequent lamp removal. v cc 14,0v 10,5v i vcc v res 1,6v i res i lvs <2,5ma 3,2v ic active softstart t t t t t < +/- 2,5ma 41a 20a 34a 17a 20a 32 cycles (>50ms typically) 16,0v transient at lvs pin fault latch set e.g. by eol v res >1,3v 0,375v 1,3v power down signal t fault latch signal t 8ma + qgate 150a 8ma + qgate ic active lamp removal ls + hs open >12a >12a >12a h h reset signal 5,0v set signal 20a <3,2v 1,6v 1,3v
ICB1FL01G state diagram preliminary datasheet version 1.5 18 june 2005 4 state diagram figure 17 state diagram 62ms 35ms 10ms 0ms ?2000ms 40ms ?235ms 250ms 500ms uvlo monitoring softstart preheating ignition pre-run run mains switch turned on; 0 < vcc < 10,5v; is< 80a; ires= 0a active active active active active act,restart active cap.load1; eol1,2 active active, & 0,8v active active overcurrent inverter 1,6v active active active (300ns) active overcurrent pfc 1,0v active (605s) capacitive load 2 active active active active bus open loop <15% (80s) bus undervoltage <75% active active active active bus overvoltage >109% active active active active active act,restart active cap.load1; eol1,2 active active, & 0,8v active active overcurrent inverter 1,6v active active active active overcurrent pfc 1,0v active capacitive load 2 active active active active bus open loop <15% bus undervoltage <75% active active active active bus overvoltage >109% 10,5 < vcc < 14,0v; is< 150a; ires= 20a vcc > 14,0v & vres< 1,6v=> start 120khz < f < f_ph; 10,5 < vcc < 16,0v; f= f_ph 10,5 < vcc < 16,0v; ires= 20a; f= f_run 10,5 < vcc < 16,0v; f_ph < f < f_run 10,5 < vcc < 16,0v; f= f_run earliest stop by eol fault mode: disabled by lamp removal or uvlo ; 10,5 < vcc < 16,0v; is< 150a; ires= 20a
ICB1FL01G protection functions preliminary datasheet version 1.5 19 june 2005 5 protection functions description of fault fault-type min. duration of effect detection active during consequence softstart 10ms preheat mode 0 - 2000ms ignition mode 40 - 235ms pre-run mode 250ms run mode +/- peak level of lamp voltage above threshold eol1 500ms x power down, latched fault mode ratio of +/- amplitudes of lamp voltage > 1.15 or < 0.85 eol2 500ms x power down, latched fault mode no zero voltage switching cap.load 1 500ms x power down, latched fault mode voltage at pin res > 3.0v open filament 500ms x power down, latched fault mode bus voltage > 109% of rated level in active operation overvoltage 500ms x power down, latched fault mode bus voltage > 109% of rated level 10s after power up overvoltage gate drivers off, restart after v cc hysteresis bus voltage > 109% of rated level in active operation pfc overvoltage 5s xxxxxturn-off pfc mosfet until bus voltage < 105% bus voltage < 75% of rated level undervoltage 80s x gate drivers off, restart after v cc hysteresis bus voltage < 15% of rated level open loop detection 1s xxxxxpower down capacitive load, operation below resonance cap.load 2 605s x x power down, latched fault mode run frequency can not be achieved no ignition 235ms x power down, latched fault mode voltage at pin res > 1.6v before power up ls open filament 1ms prevents power up current into pin lvs1 < 12a hs open filament 1ms prevents power up current into pin lvs2 < 12a hs open filament 1ms prevents power up voltage at pin pfccs > 1.0v pfc overcurrent 260nsxxxxxturn-off pfc mosfet immediately voltage at pin lscs > 0.8v inverter current limit 250ns x increases the operating frequency voltage at pin lscs > 1.6v inverter overcurrent 400nsxxxxxpower down, latc hed fault mode supply voltage at pin vcc < 14.0v before power up below startup threshold 1s prevents power up supply voltage at pin vcc < 10.5v after power up below uvlo threshold 1s xxxxxpower down, reset of latched fault mode
ICB1FL01G electrical characteristics preliminary datasheet version 1.5 20 june 2005 6 electrical characteristics note: all voltages without the high side signals are measured with respect to ground (pin 4). the high side voltages are measured with respect to pin17/20. the voltage levels are valid if other ratings are not violated. 6.1 absolute maximum ratings note: absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. for the same reason make sure, that any capacitor that will be connected to pin 3 ( v cc) and pin 18 (hsvcc) is discharged before assembling the application circuit. parameter symbol limit values unit remarks min. max. lscs voltage v lscs -5 6 v lscs current i lscs -3 3 ma lsgd voltage v lsgd -0.3 v cc +0.3 v internally clamped to 11v vcc voltage v vcc -0.3 18 v see vcc zener clamp vcc zener clamp current i vcczener -5 5 ma ic in power down mode pfcgd voltage v pfcgd -0.3 v cc +0.3 v internally clamped to 11v pfccs voltage v pfccs -5 6 v pfccs current i pfccs -3 3 ma pfczcd voltage v pfczcd -3 6 v pfczcd current i pfczcd -5 5 ma pfcvs voltage v pfcvs -0.3 5.3 v rfrun voltage v rfrun -0.3 5.3 v rfph voltage v rfph -0.3 5.3 v rtph voltage v rtph -0.3 5.3 v res voltage v res -0.3 5.3 v lvs1 current1 i lvs1_1 -1 1 ma ic in power down mode lvs1 current2 i lvs1_2 -3 3 ma ic in active mode lvs2 current1 i lvs2_1 -1 1 ma ic in power down mode lvs2 current2 i lvs2_2 -3 3 ma ic in active mode hsgnd voltage v hsgnd -900 900 v referring to gnd hsgnd, voltage transient dv hsgnd /dt -40 40 v/ns hsvcc voltage v hsvcc -0.3 18 v referring to hsgnd hsgd voltage v hsgd -0.3 v hsvcc + 0.3 v internally clamped to 11v referring to hsgnd pfcgd peak source current i pfcgdsomax ? 150 ma < 100ns pfcgd peak sink current i pfcgdsimax ? 700 ma < 100ns lsgd peak source current i lsgdsomax ? 75 ma < 100ns lsgd peak sink current i lsgdsimax ? 400 ma < 100ns hsgd peak source current i hsgdsomax ? 75 ma < 100ns
ICB1FL01G electrical characteristics preliminary datasheet version 1.5 21 june 2005 6.2 operating range. hsgd peak sink current i hsgdsimax ? 400 ma < 100ns junction temperature t j -25 150 c storage temperature t s -55 150 c total power dissipation p tot ? t.b.d w pg-dso-18-1, t amb = 25c thermal resistance (both chips) junction-ambient r thja ? t.b.d k/w pg-dso-18-1 thermal resistance (hs chips) junction-ambient r thjahs ? 120 k/w pg-dso-18-1 thermal resistance (ls chips) junction-ambient r thjals ? 120 k/w pg-dso-18-1 soldering temperature 260 c wave sold. acc.jesd22a111 esd capability v esd ? 2 kv human body model 1) 1) according to eia/jesd22-a114-b (discharging an 100pf capacitor through an 1.5k ? series resistor). parameter symbol limit values unit remarks min. max. hsvcc supply voltage v hsvcc v hsvccoff 17.0 v referring to hsgnd hsgnd supply voltage v hsgnd -900 900 v referring to gnd vcc supply voltage v vcc v vccoff 17.5 v lscs voltage range v lscs -4 5 v pfcvs voltage range v pfcvs 04v pfccs voltage range v pfccs -4 5 v pfczcd current range i pfczcd -4 4 ma lvs1, lvs2 voltage range v lvs1,lvs2 -0.3 1) 1) limited by maximum of current range at lvs1, lvs2 v ic in power down mode lvs1, lvs2 current range i lvs1,lvs2 2) 2) limited by minimum of voltage range at lvs1, lvs2 300 a ic in power down mode lvs1, lvs2 current range i lvs1,lvs2 -2.5 2.5 ma ic in active mode junction temperature t j -25 125 c adjustable preheating frequency range set by rfph f rfph f rfrun 150 khz adjustable run frequency range set by rfrun f rfrun 20 100 khz adjustable preheating time range set by rtph t rtph 01980ms set resistor for run frequency r frun 525k ? set resistor for preheating frequency (r frun parallel r fph ) r frun ii r fph 3.3 k ? set resistor for preheating time r tph 020k ?
ICB1FL01G electrical characteristics preliminary datasheet version 1.5 22 june 2005 6.3 characteristics 6.3.1 power supply section note: the electrical characteristics involve the spread of values given within the specified supply voltage and junction temperature range t j from ? 25 c to 125 c. typical values represent the median values, which are related to 25c. if not otherwise stated, a supply voltage of v cc = 15 v and v hsvcc = 15v is assumed and the ic operates in active mode. furthermore all voltages are referring to gnd if not otherwise mentioned. parameter symbol limit values unit test condition min. typ. max. high side leakage current i hsgndleak 0.01 2 a v hsgnd = 800v v gnd = 0v vcc quiescent current i vccqu1 80 120 a v vcc = v vccoff - 0.5v vcc quiescent current i vccqu2 110 150 a v vcc = v vccon - 0.5v vcc supply current with inactive gates i vccsup1 57mav pfcvs > 2.725v vcc supply current in latched fault mode i vcclatch ?110170av res = 5v ls vcc turn-on threshold ls vcc turn-off threshold lsvcc turn-on/off hysteresis v vccon v vccoff v vcchys 13.6 10.0 3.3 14.1 10.5 3.6 14.6 11.0 3.9 v v v vcc zener clamp voltage v vccclmp 15.716.316.9v i vcc = 2ma v res = 5v vcc zener clamp current i vcczener 2.5 ? 5 ma v vcc = 17.5v v res = 5v hsvcc quiescent current i hsvccqu 1) 1) with reference to high side ground hsgnd ? 170 250 a v hsvcc = v hsvccon -0.5v hsvcc supply current with inactive gate i hsvccsup1 1) ? 0.65 1.2 ma hsvcc turn-on threshold hsvcc turn-off threshold hsvcc turn-on/off hysteresis v hsvccon 1) v hsvccoff 1) v hsvcchys 1) 9.6 7.9 1.4 10.1 8.4 1.7 10.6 8.9 2.0 v v v
ICB1FL01G electrical characteristics preliminary datasheet version 1.5 23 june 2005 6.3.2 pfc section 6.3.2.1 pfc current sense (pfccs) 6.3.2.2 pfc zero current detector (pfczcd) 6.3.2.3 pfc bus voltage sense (pfcvs) parameter symbol limit values unit test condition min. typ. max. turn-off threshold v pfccsoff 0.95 1.0 1.05 v spike blanking t blanking 200 260 320 ns pfccs bias current i pfccsbias -0.5 0.5 a v pfccs = 1.5v parameter symbol limit values unit test condition min. typ. max. zero crossing upper threshold v pfczcdup 1.41.51.6v zero crossing lower threshold v pfczcdlow 0.40.50.6v zero crossing hysteresis v pfczcdhys 1.0 v clamping of positive voltages v pfczcdpclp 5.06.37.0v i pfczcd = 4ma clamping of negative voltages v pfczcdnclp -3.5 -2.9 -2.0 v i pfczcd = 4ma pfczcd bias current i pfczcdbias -0.5 0.5 a v pfczcd = 1.7v pfczcd ringing suppression time t ringsup 450 850 ns parameter symbol limit values unit test condition min. typ. max. trimmed reference voltage v pfcvsref 2.47 2.5 2.53 v overvoltage upper detection limit v pfcvsup 2.675 2.725 2.78 v overvoltage lower detection limit v pfcvslow 2.57 2.625 2.67 v overvoltage hysteresis v pfcvshys 100 mv undervoltage detection limit v pfcvsuv 1.79 1.83 1.87 v undervoltage shut down v pfcvssd 0.30 0.375 0.45 v bias current (esd-stress<1kv) i pfcvsbias -1 1 a v pfcvs = 2.5v bias current (esd-stress>1kv) i pfcvsbias -2.5 2.5 a v pfcvs = 2.5v
ICB1FL01G electrical characteristics preliminary datasheet version 1.5 24 june 2005 6.3.2.4 pfc pwm generation 6.3.2.5 pfc gate drive (pfcgd) parameter symbol limit values unit test condition min. typ. max. initial on-time t pfcon-initial 0.61 1.4s v pfczcd = 0v max. on-time t pfcon-max 19 23.5 28 s 0.45v < v pfcvs < 2.45v repetition time when missing zero crossing t pfcrep 45 55 66 s v pfczcd = 0v off-time when missing zcd signal t pfcoff 35 42 49 s parameter symbol limit values unit test condition min. typ. max. pfcgd low voltage v pfcgdlow 0.4 0.7 0.9 v i pfcgd = 5ma 0.4 0.75 1.1 v i pfcgd = 20ma -0.1 0.3 0.6 v i pfcgd = -20ma pfcgd high voltage v pfcgdhigh 10.2 11 11.5 v i pfcgd = -20ma 9.0 ? ? v i pfcgd = -1ma v vcc = v vccoff + 0.3v 8.5 ? ? v i pfcgd = -5ma v vcc = v vccoff + 0.3v pfcgd voltage active shut down v pfcgdsd 0.4 0.75 1.1 v i pfcgd = 20ma v vcc = 5v pfcgd peak source current i pfcgdsource ?100?mar load = 4 ? + c load = 3.3nf 1) 1) the parameter is not subject to production test - verified by design/characterization pfcgd peak sink current i pfcgdsink ?-500? mar load = 4 ? + c load = 3.3nf 1) pfcgd rise time 2v < v lsgd < 8v t pfcgdrise 110 220 400 ns r load = 4 ? + c load = 3.3nf pfcgd fall time 8v > v lsgd > 2v t pfcgdfall 20 45 70 ns r load = 4 ? + c load = 3.3nf
ICB1FL01G electrical characteristics preliminary datasheet version 1.5 25 june 2005 6.3.3 inverter section 6.3.3.1 inverter control (rfrun, rfph, rtph) 6.3.3.2 inverter low side current sense (lscs) parameter symbol limit values unit test condition min. typ. max. fixed start-up frequency f startup 112 125 138 khz duration of soft start, shift f from start-up to preheating frequency t softstart 9.0 11.0 13.5 ms preheating frequency f rfph1 97.5 100 102.5 khz r rfph = 10k ? r rfrun = 10k ? run frequency f rfrun1 49.0 50.0 51.0 khz r rfrun = 10k ? preheating time t rtph1 700 1000 1300 ms r rtph = 8.06k ? 1) preheating time t rtph2 55 100 145 ms r rtph = 806 ? 1) current source preheating time i rtph 110 140 170 a min. duration of ignition, shift f from preheating to run frequency 40 ms 1) 1) the parameter is not subject to production test - verified by design/characterization max. duration of ignition, shift f from preheating to run frequency 235 ms 1) duration of pre-run, time period after operating frequency has reached run frequency first time after ignition 250 ms 1) minimum duration of fault condition by eol1, eol2, cap.load 1, open filament and overvoltage for entering latched fault mode 500 ms 1) minimum duration of fault condition by cap.load 2 for entering latched fault mode t capload2 520 610 750 s 1) parameter symbol limit values unit test condition min. typ. max. current limit threshold during ignition mode v lscslimit 0.76 0.80 0.84 v duration of current above threshold for enabling frequency increase t lscslimit 200 250 320 ns overcurrent shut down threshold v lscsovc 1.55 1.60 1.65 v duration of overcurrent for entering latched fault mode t lscsovc 320 400 480 ns bias current lscs i lscsbias -0.5 0.5 a v lscs = 1.5v inverter dead time between ls off and hs on t deadtime 1.50 1.75 2.0 s
ICB1FL01G electrical characteristics preliminary datasheet version 1.5 26 june 2005 6.3.3.3 restart after lamp removal (res) 6.3.3.4 lamp voltage sense (lvs1, lvs2) parameter symbol limit values unit test condition min. typ. max. low-side open filament threshold v resofil 3.13.23.3v capacitive load detection threshold v rescap 0.18 0.24 0.30 v discharge resistor during latched fault mode r resdisch 40 54 70 k ? i1 current source i res1 -54.3 -41 -29.5 a v res =1v; lvs1=5a i2 current source i res2 -46 -34 -24.2 a v res =2v; lvs1=5a i3 current source i res3 -27.6 -20 -15.1 a v res =1v; lvs1=50a i4 current source i res4 -22.6 -17 -12.3 a v res =2v; lvs1=50a c1 comparator threshold v resc1 1.55 1.6 1.65 v c2 comparator threshold v resc2 1.26 1.3 1.34 v c3 comparator threshold v resc3 0.32 0.375 0.46 v parameter symbol limit values unit test condition min. typ. max. source current before start up i lvssource -8 -5 -2 a 11 < v vcc < 13v v lvs = 0v threshold for enabling lamp monitoring v lvsenable 1.52.33.0v 11 < v vcc < 13v sink current threshold for lamp detection i lvssink 91526av lvs > v vcc positive eol current threshold i lvspeol 190 230 265 a t > 0c negative eol current threshold i lvsneol -265 -230 -190 a t > 0c maximum ratio between positive and negative current amplitude 1) 1) ro lvs1max ro lvs2max 1.1 1.2 1.3 i lvssourpeak =150a i lvssinkpeak = increasing minimum ratio between positive and negative current amplitude 1) ro lvs1min ro lvs2min 0.75 0.85 0.95 i lvssinkpeak =150a i lvssourcepeak = increasing positive clamping voltage i lvsclmp -v vcc + 1v -vi lvs = 300a ro lvs i lvs kpeak sin n1 + () i lvssourcepeak n () -------------------------------------------------------- = ro lvs i lvssource n2 + () i lvs kp sin eak n1 + () -------------------------------------------------------- =
ICB1FL01G electrical characteristics preliminary datasheet version 1.5 27 june 2005 6.3.3.5 inverter low side gate drive (lsgd) parameter symbol limit values unit test condition min. typ. max. lsgd low voltage v lsgdlow 0.4 0.7 1.0 v i lsgd = 5ma 0.5 0.8 1.2 v i lsgd = 20ma -0.3 0.1 0.4 v i lsgd = -20ma lsgd high voltage v lsgdhigh 10.0 10.8 11.4 v i pfcgd = -20ma 9.0 ? ? v i pfcgd = -1ma v vcc = v vccoff + 0.3v 8.5 ? ? v i pfcgd = -5ma v vcc = v vccoff + 0.3v lsgd voltage active shut down v lsgdsd 0.5 0.8 1.2 v i hsgd = 20ma v hsvcc = 5v lsgd peak source current i lsgdsource ?50?mar load = 10 ? + c load = 1nf 1) 1) the parameter is not subject to production test - verified by design/characterization lsgd peak sink current i lsgdsink ?-300? mar load = 10 ? + c load = 1nf 1) lsgd rise time 2v < v lsgd < 8v t lsgdrise 110 220 400 ns r load = 10 ? + c load = 1nf lsgd fall time 8v > v lsgd > 2v t lsgdfall 20 35 60 ns r load = 10 ? + c load = 1nf
ICB1FL01G electrical characteristics preliminary datasheet version 1.5 28 june 2005 6.3.3.6 inverter high side gate drive (hsgd) parameter symbol limit values unit test condition min. typ. max. hsgd low voltage v hsgdlow 0.02 0.05 0.1 v i hsgd = 5ma 0.5 1.1 2.5 v i hsgd = 100ma -0.4 -0.2 -0.05 v i hsgd = -20ma hsgd high voltage v hsgdhigh 9.5 10.5 11.0 v i hsgd = -20ma 7.8 ? ? v i hsgd = -1ma v hsvcc = v hsvccoff + 0.3v hsgd voltage active shut down v hsgdsd 0.05 0.22 0.50 v i hsgd = 20ma v hsvcc = 5v hsgd peak source current i hsgdsource ?50?mar load = 10 ? + c load = 1nf 1) 1) the parameter is not subject to production test - verified by design/characterization hsgd peak sink current i hsgdsink ?-300? mar load = 10 ? + c load = 1nf 1) hsgd rise time 2v < v hsgd < 8v t hsgdrise 150 220 300 ns r load = 10 ? + c load = 1nf hsgd fall time 8v > v hsgd > 2v t hsgdfall 20 35 70 ns r load = 10 ? + c load = 1nf
ICB1FL01G application examples preliminary datasheet version 1.5 29 june 2005 7 application examples 7.1 operating behaviour of a ballast for a single fluorescent lamp after turning on the mains switch the peak value of the rectified ac input voltage is available at c02 and smoothing capacitor c10 (fig. 18). via r11 and r12 the supply voltage increases at bypass capacitors c12 and c13. at a level of 10,5v a source current out of pin res is sensing the existence of the low-side filament of the fluorescent lamp. fed from the bus voltage a current is detected at pin lvs1 via r31...r35, when the high-side filament is connected. the current fed into pin lvs1 is used to charge c12 via internal clamping diode. the ic changes into active mode when vcc level achieves the turn-on threshold of 14v and both filaments are detected. if not required the pin lvs2 can be disabled by connecting to gnd. the active ic is sensing the bus voltage level via r14, r15. gate drives are disabled when open loop or overvoltage are detected. if bus voltage level is within the allowed range, the low-side gate drive is starting with the first pulse of the 120khz softstart frequency. only few cycles are requir ed to charge the bootstrap capacitor c14 via d6, r30 and q3. without r30 there is a risk of overcurrent shut down by exceeding the 1,6v threshold at pin lscs. the power supply is generated by a charge pump c16, d7 and d8. in normal operation c16 is charged and discharged via c17 from the current forced by the resonance inductor l2 during the deadtime of the inverter producing a zero voltage switching (zvs) operation. run frequency, preheating frequency and preheating time are set by resistors r21, r22 and r23. figure 18 application circuit of a ballast for a single fluorescent lamp with voltage mode preheating. during run mode the lamp voltage is sensed via r31...r33 in order to detect an abnormal increasing of lamp voltage or an rectifier effect that can occur at end-of-life conditions of the lamp. at the pin res there is also detected a non-zvs operation, classified into capmode1 and capmode2. this will be done by the capacitive divider c18, c19, that transfers the divided ac-part of the inverter output voltage to pin res. dependent on the shape of the signal two different time windows can be started at abnormal conditions in order to protect the ballast. d10 limits voltage transients that can occur during removal of the lamp. voltage mode preheating is done by two separate windings on the resonant inductor l2. the bandpass filters l21, c21 and l22, c22 are designed to pass preheating current at preheating frequency only and to block any current during run mode. ignition is provided by shifting the operating frequency towards the resonant frequency of l2 and c20. the voltage level during ignition is limited by the current sensed at shunt resistors r24, r25 with a level of 0,8v at pin lscs. overcurrents that exceed a voltage level of 1,6v for longer than 400ns will disable the ic at any time and change into fault mode. the pfc preconverter with l1, q1 and d5 is starting with a fixed frequent operation and change over to a critical conduction mode (critcm) as soon as the level at pin pfczcd is sufficient to trigger the operation. during light load the operation mode changes into discontinuous conduction mode (dcm). compensation of the voltage control loop is completely integrated with a digital filter and error amplifier. pfc overcurrent is sensed by r18, r19, bus overvoltage and undervoltage at pin pfcvs. rfrun rfph rtph vcc pfczcd pfcgd pfcvs pfccs hsgd hsvcc hsgnd lsgd lscs lvs2 res gnd 90v... 270v ac ICB1FL01G r11 r12 d1...4 l0 l1 d5 q1 r15 r14 r13 r16 r18 d9 c01 c10 c11 r19 r21 r22 r23 r26 r27 c14 c13 q2 q3 r24 r35 r34 r31 r32 r33 r36 c17 c16 c18 c19 c20 l2 d6 d7 d8 r29 c12 lvs1 c21 c22 l21 l22 f1 c02 c05 c04 c03 pe c15 r20 r25 n1 n2 n3 k1 k2 k3 k4 r30 k01 k02 k03 d10
ICB1FL01G application examples preliminary datasheet version 1.5 30 june 2005 7.2 design equations of a ballast application subsequent the design equations are listed: start-up resistors r11, r12: selected value: r11= 470k; r12= 470k current limitation resistor r13 of pfc zero current detector (pfczcd). the additional factor 2 is used in order to keep away from limit value. selected value: r13= 33k. pfc voltage sense resistor r20 selected value: r20= 10k pfc voltage sense resistors r14, r15 selected values: r14= 820k; r15= 820k low pass capacitor c11 selected corner frequency f c1 = 10khz. selected value c3= 2,2nf pfc shunt resistors r18, r19 selected values: r18= 2,2ohm; r19= 2,2ohm set resistor r21 for run frequency, at a projected run frequency of 40khz selected value: r21= 12,4k r 11 r 12 + v inmin i vccqu2 ------------------------- 200v 150 a ----------------- 1 3 3 m ? , === r 13 v bus n sec 2 ?? i pfczcd n prim 1 ?? ----------------------------------------------------------- 410v 31 2 ?? 4ma 162 1 ?? --------------------------------- 3 9 k ? === r 20 v ref 100 i pfcbias ? ------------------------------------------ 250v , 100 2 5 a , ? ------------------------------ -10k ? == r 14 r 15 + v bus v ref ? v ref --------------------------------------- r 20 ? 410v 2 5v , () ? 25v , ------------------------------------- -10k ? 1630k ? === c 11 1r 20 r 14 r 15 ++ () ? 2 f c1 r 20 r 14 r 15 + () ?? ? ? --------------------------------------------------------------------------- 1 10k 820k 820k ++ () ? 2 10khz 10k 820k 820k + () ?? ? ? -------------------------------------------------------------------------------------- - 1 60nf , == =
ICB1FL01G application examples preliminary datasheet version 1.5 31 june 2005 set resistor r22 for preheating frequency, at a projected preheating frequency of 95khz selected value: r22= 9,1k set resistor r23 for preheating time, at a projected preheating time of 1000ms selected value: r23= 8,2k gate drive resistors r16, r26, r27 are recommended to be equal or higher than 10ohm. shunt resistors r24, r25 the selected lamp type 54w-t5 requires an ignition voltage of v ign = 800v peak. in our application example the resonant inductor is evaluated to l2= 1,46mh and the resonant capacitor c20= 4,7nf. with this inputs we can calculate the ignition frequency f ign : r 18 r 19 ? r 18 r 19 + -------------------------- v pfccsoff v inacmin 2 ?? ? 4p outpfc ? ---------------------------------------------------------------------------------------------- 1v 0 95 , 180v 2 ?? ? 455w ? ----------------------------------------------------- -11 ? , === r 21 r frun 510 8 ? hz ?? f run --------------------------------- 510 8 ? hz ?? 40khz --------------------------------- 1 2 5 k ? , ==== r 22 r fph r frun f ph r frun ? 510 8 ? hz ?? ------------------------------------ 1 ? --------------------------------------------- 12 4k , 95khz 12 4k , ? 510 8 ? hz ?? ------------------------------------ -1 ? ---------------------------------------------- 9 1 4 k ? , == = = r 23 r tph t ph ms [] 125ms () k ? () ? -------------------------------------- 1000ms 125ms () k ? () ? -------------------------------------- 8 0 k ? , == = = f ign 1 v bus 2 ? v ign ? ------------------------ 4 2 l 2 c 20 ??? --------------------------------------- - 1 410v 2 ? 800v ? --------------------- 4 2 146mh , 4 7nf , ?? ? ------------------------------------------------------------ - 69759hz == =
ICB1FL01G application examples preliminary datasheet version 1.5 32 june 2005 the second solution of this equation (with the minus sign) leads to a result of 50163hz, which is on the capacitive side of the resonant rise. this value is no solution, because the operating frequency approaches from the higher frequency level. in the next step we can calculate the current through the resonant capacitor c20 when reaching a voltage level of 800v peak. finally the resistors r24, r25 can be calculated from ic20 and the current limitation threshold during ignition mode. selected values are r24= 0,82ohm; r25= 0,82ohm. lamp voltage sense resistors r31, r32, r33 the selected lamp type 54w-t5 has a typical run voltage of 167v peak. we decide to set the eol-thresholds at a level of 1,5 times the run voltage level (= 250,5v peak). selected values: r31= 330k; r32= 390k; r33= 390k current source resistors r34, r35 for detection of high-side filament selected values: r34= 2,2m; r35= 2,2m; current limitation resistor r30 for floating bootstrap capacitor c14 a factor of 2 is provided in order to keep current level significant below lscs turn-off threshold. selected value: r30= 10ohm. low-side filament sense resistor r36 for a single lamp ballast selected value: r36= 56k i c20 v ign 2 f ign c 20 ??? ? 800v 2 69759hz 4 7nf , ??? ? 165a , == = r 24 r 25 ? r 24 r 25 + -------------------------- v lscslimit i c20 -------------------------------------- - 08v , 165a , ---------------- 0 4 8 5 ? , === r 31 r 32 r 33 ++ v leol i lvseol --------------------------- 250 5v , 230 a ------------------- 1 0 8 9 k ? === r 34 r 35 + v inmin i lvssinkmax --------------------------------------------- r 31 r 32 r 33 ++ () ? 200v 22 a -------------- 1110k () ? 7980k ? === r 30 2v ccon ? v lscsovc --------------------------------- - r 24 r 25 ? r 24 r 25 + -------------------------- ? 214v ? 16v , ----------------- - 082 , 082 , ? 082 , 082 , + ----------------------------- - ? 718 ? , == r 36 v resc1min i res3min ------------------------------------ - 155v , 27 6 a , -------------------- 5 6 1 6 k ? , ==
ICB1FL01G application examples preliminary datasheet version 1.5 33 june 2005 selected values in a topology with 2 lamps in parallel: r36a= 110k; r36b= 110k low pass filter capacitor c19 capacitor c19 provides a low pass filter together with resistor r36 in order to suppress ac voltage drop at the low-side filament. when we estimate an ac voltage of 10v peak-to-peak at low-side filament during run mode at f run = 40khz, we need a suppression of a factor f lp = 100 (-40db). selected value: c19= 15nf detection of capacitive mode operation via c18 the dc level at pin res is set by r36 and the source current i res3 . the preferred ac level is in the range between ? v acres = 1,5v to 2,0v at a ? v bus = 410v. selected value: c18= 68pf. bandpass filters l21/c21 and l22/c22 can be used in order to conduct filament currents preferred at preheating frequency and to suppress these currents during run mode. inductor l1 of the boost converter the inductivity of the boost inductor typically is design ed to operate within a specified voltage range above a minimum frequency in order to get an easier rfi suppression. it is well known, that in critical conduction mode (critcm) there is a minimum operating frequency at low input voltages and another minimum at maximum input voltage. in state-of-the-art critcm pfc controllers we use the lowest value out of these two criterias: at minimum ac input voltage: at maximum ac input voltage r 36a v resc1max i res3min --------------------------------------- 165v , 15 1 a , -------------------- 1 0 9 3 k ? , == c 19 f lp 2 1 ? 2 f run r 36 ?? ? () -------------------------------------------------- 100 2 1 ? 2 40khz 56k ?? ? () --------------------------------------------------- 7 1 n f , == = c 18 c 19 ? v acres ? v bus ----------------------------- ? 15nf 2v 410v ------------- ? 73pf === l a v inacmin 2 ? () 2 v bus v inacmin 2 ? () ? () ?? 4f min p outpfc v bus ?? ? ------------------------------------------------------------------------------------------------------------------------------- ---------------- - =
ICB1FL01G application examples preliminary datasheet version 1.5 34 june 2005 with the new control principle for the pfc preconverter we have a third criteria that covers the maximum on-time t pfcom-max = 23,5s: with the assumed conditions the lowest value out of l a , l b , l c is 1,44mh. selected value: l1= 1,44mh. l a 180v 2 ? () 2 410v 180v 2 ? () ? () 095 , ?? 4 30khz 55w 410v ??? ------------------------------------------------------------------------------------------------------------- 3 5 4 m h , == l b v inacmax 2 ? () 2 v bus v inacmax 2 ? () ? () ?? 4f min p outpfc v bus ?? ? ------------------------------------------------------------------------------------------------------------------------------- --------------------- - = l b 270v 2 ? () 2 410v 270v 2 ? () ? () 095 , ?? 4 30khz 55w 410v ??? ------------------------------------------------------------------------------------------------------------- 1 4 4 m h , == l c v inacmin 2 ? () t onmax ?? 4p outpfc ? ------------------------------------------------------------------------------------------ - = l c 180 2 ? () 23 5 s , 095 , ?? 455w ? ---------------------------------------------------------------- -658mh , ==
ICB1FL01G application examples preliminary datasheet version 1.5 35 june 2005 bill of material for the application circuit of figure 18 and the design equations standing ahead. this design was used as an evaluation board. table 1 bill of material for a fl-ballast of a 54w-t5 lamp f1 fuse 1a fast c17 150nf/630v ic1 icb1lb01g c18 68pf/1kv q1 spp03n60c3 (600v/1,4 ? ) c19 15nf/63v q2 spp03n60c3 (600v/1,4 ? ) c20 4,7nf/1600v dc q3 spp03n60c3 (600v/1,4 ? ) c21 22nf/400v d1...d4 b250c1000 c22 22nf/400v d5 mur160 d6 mur160 r11 470k d7 uf4003 r12 470k d8 uf4003 r13 33k d9 bzx79c16 r14 820k r15 820k l0 2x56mh/0,5a r16 33 l1 1,44mh; e25/13/7 r18 2,2 np/ns= 162/31 r19 2,2 l2 1,46mh; ev25/13/13 r20 10k np/ns= 174/5 r21 12,4k (40,3khz) l21 125h; e13/7/4 r22 9,1k (95,27khz) l22 125h; e13/7/4 r23 8,2k (1025ms) c01 220nf/x2/275v ac r24 0,82 c02 220nf/x2/275v ac r25 0,82 c03 3,3nf/y1/400v ac r26 33 c10 10f/450v dc r27 33 c11 2,2nf/63v r30 10 c12 470nf/63v r31 330k c13 470nf/63v r32 390k c14 100nf/63v r33 390k c15 150nf/630v r34 2,2m c16 1nf/1kv r35 2,2m r36 56k
ICB1FL01G application examples preliminary datasheet version 1.5 36 june 2005 7.3 multilamp ballast topologies how to use ICB1FL01G in multi-lamp topologies is demonstrated in the subsequent figures. in figure 19 we see an application for a single lamp with current mode preheating. compared with figure 18 the difference is the connection of the resonant capacitor in series with the filaments. in respect of operating behaviour the current mode preheating cannot be designed with same variation of operating parameters: the preheating current is typically lower and lamp voltage during preheating higher than in topologies with current mode preheating. figure 19 application circuit of a ballast for a single fluorescent lamp with current mode preheating. a topology for two lamps is shown in figure 20. both lamps including their individual resonant circuit are operating in parallel at the same inverter output. such a topology can be done with voltage mode preheating in the same way. as the control ic is designed to operate such a 2-lamp topology without restrictions in respect to the monitoring functions, the ic-specific effort is to activate the second lamp voltage sense (lvs2) and an additional resistor at pin res in order to sense the lamp removal of the second low-side filament. figure 20 application circuit of a ballast for two fluorescent lamps in parallel with current mode preheating. beside a topology with paralleled lamps it is possible of course to use two lamps in series. in this way we come to a 4-lamp topology shown in figure 21. the lamp voltage is sensed of each of the two series connections. the rf run rf ph rt ph vcc pfczcd pfcgd pfcvs pfccs hsgd hsvcc hsgnd lsgd lscs lvs2 lvs1 gnd 90 ... 270 vac ICB1FL01G res rf run rf ph rt ph vcc pfczcd pfcgd pfcvs pfccs hsgd hsvcc hsgnd lsgd lscs lvs2 lvs1 gnd 90 ... 270 vac ICB1FL01G res
ICB1FL01G outline dimension preliminary datasheet version 1.5 37 june 2005 lamp removal is detected on the high-side filaments of the high-side lamps and on the low-side filaments of the low-side lamps. in this way icb1lb01g supports multi-lamp topologies with all required monitoring functions with a low number of external components. figure 21 application circuit of a ballast for four fluorescent lamps with voltage mode preheating. 8 outline dimension rfrun rfph rtph vcc pfczcd pfcgd pfcvs pfccs hsgd hsvcc hsgnd lsgd lscs lvs2 lvs1 gnd 90 ... 270 vac ICB1FL01G res -0.2 index marking 1 10 +0.15 0.35 0 . 2 0.2 20 2) 11 20x 2 . 4 5 2 . 6 5 m a x . 0.1 10.3 - 0 . 1 - 0 . 2 7.6 0.3 1) does not include plastic or metal protrusions of 0.15 max per side 2) 1) does not include dambar protrusion of 0.05 max per side 1.27 0 . 2 3 + 0 . 0 9 m a x . 8 0.35 x 45 +0.8 0.4 12.8 -0.2 1) pg-dso-18-1 (plastic dual small outline)
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